The automotive chip industry is undergoing changes
Recently, the semiconductor engineering team discussed small chips, hybrid bonding, and new materials with Michael Kelly, Vice President of Amkor's small chip and FCBGA integration. Also participating in the discussion were ASE researcher William Chen, Promex Industries CEO Dick Otte, and Sander Roosendaal, R&D Director of Synopsys Photonics Solutions. Below are excerpts from this discussion.
For many years, the development of automotive chips did not take a leading position in the industry. However, with the rise of electric vehicles and the development of advanced infotainment systems, this situation has changed dramatically. What issues have you noticed?
Kelly: High-end ADAS (Advanced Driver Assistance Systems) requires processors with a 5-nanometer process or smaller to be competitive in the market. Once you enter the 5-nanometer process, you have to consider wafer costs, which leads to careful consideration of small chip solutions, as it is difficult to manufacture large chips at the 5-nanometer process. Additionally, the yield is low, resulting in extremely high costs. When dealing with 5-nanometer or more advanced processes, customers typically consider selecting a portion of the 5-nanometer chip rather than using the entire chip, while increasing investment in the packaging stage. They might think, "Would it be a more cost-effective option to achieve the required performance this way, rather than trying to complete all functions in a larger chip?" So, yes, high-end automotive companies are definitely paying attention to small chip technology. Leading companies in the industry are closely monitoring this. Compared to the computing field, the automotive industry is probably 2 to 4 years behind in the application of small chip technology, but the trend for its application in the automotive sector is clear. The automotive industry has extremely high reliability requirements, so the reliability of small chip technology must be proven. However, large-scale application of small chip technology in the automotive field is certainly on the way.
Chen: I haven't noticed any significant obstacles. I think it’s more about needing to learn and understand the relevant certification requirements in depth. This goes back to the metrology level. How do we manufacture packages that meet the extremely stringent automotive standards? But it is certain that the relevant technology is continuously evolving.
Given the many thermal issues and complexities associated with multi-die components, will there be new stress test profiles or different types of tests? Can the current JEDEC standards cover such integrated systems?
Chen: I believe we need to develop more comprehensive diagnostic methods to clearly identify the source of failures. We have discussed combining metrology with diagnostics, and we have a responsibility to figure out how to build more robust packages, use higher quality materials and processes, and validate them.
Kelly: Nowadays, we are conducting case studies with customers, who have learned something from system-level testing, especially temperature impact testing in functional board tests, which is not covered in JEDEC testing. JEDEC testing is merely isothermal testing, involving "temperature rise, fall, and temperature transition." However, the temperature distribution in actual packages is far from what occurs in the real world. More and more customers want to conduct system-level testing early because they understand this situation, although not everyone is aware of it. Simulation technology also plays a role here. If one is skilled in thermal-mechanical combination simulation, analyzing problems becomes easier because they know what aspects to focus on during testing. System-level testing and simulation technology complement each other. However, this trend is still in its early stages.
Are there more thermal issues to address at mature technology nodes than in the past?
Otte: Yes, but in the past couple of years, coplanarity issues have become increasingly prominent. We see 5,000 to 10,000 copper pillars on a chip, spaced between 50 microns and 127 microns apart. If you closely examine the relevant data, you will find that placing these copper pillars on the substrate and performing heating, cooling, and reflow soldering operations requires achieving about one part in a hundred thousand coplanarity precision. One part in a hundred thousand precision is like finding a blade of grass within the length of a football field. We have purchased some high-performance Keyence tools to measure the flatness of the chip and substrate. Of course, the ensuing question is how to control this warping phenomenon during the reflow soldering cycle? This is a pressing issue that needs to be addressed.
Chen: I remember discussions about Ponte Vecchio, where they used low-temperature solder for assembly considerations rather than performance reasons.
Given that all the circuits nearby still have thermal issues, how should photonics be integrated into this?
Roosendaal: Thermal simulation needs to be conducted for all aspects, and high-frequency extraction is also necessary because the signals entering are high-frequency signals. Therefore, issues like impedance matching and proper grounding need to be addressed. There can be significant temperature gradients, which may exist within the die itself or between what we call the "E" die (electrical die) and the "P" die (photon die). I'm curious if we need to delve deeper into the thermal characteristics of adhesives.
This raises discussions about bonding materials, their selection, and stability over time. It is evident that hybrid bonding technology has been applied in the real world, but it has not yet been used for mass production. What is the current state of this technology?
Kelly: All parties in the supply chain are paying attention to hybrid bonding technology. Currently, this technology is mainly led by foundries, but OSAT (Outsourced Semiconductor Assembly and Test) companies are also seriously studying its commercial applications. Classic copper hybrid dielectric bonding components have undergone long-term validation. If cleanliness can be controlled, this process can produce very robust components. However, it has extremely high cleanliness requirements, and the capital equipment costs are very high. We experienced early application attempts in AMD's Ryzen product line, where most of the SRAM used copper hybrid bonding technology. However, I haven't seen many other customers applying this technology. Although it is on the technology roadmaps of many companies, it seems that it will take a few more years for the related equipment suites to meet independent cleanliness requirements. If it can be applied in a factory environment with slightly lower cleanliness than a typical wafer fab, and if lower costs can be achieved, then perhaps this technology will receive more attention.
Chen: According to my statistics, at least 37 papers on hybrid bonding will be presented at the 2024 ECTC conference. This is a process that requires a lot of expertise and involves a significant amount of fine operations during assembly. So this technology will definitely see widespread application. There are already some application cases, but in the future, it will become more prevalent across various fields.
When you mention "fine operations," are you referring to the need for significant financial investment?
Chen: Of course, it includes time and expertise. Performing this operation requires a very clean environment, which necessitates financial investment. It also requires related equipment, which similarly requires funding. So this involves not only operational costs but also investment in facilities.
Kelly: In cases with a spacing of 15 microns or larger, there is significant interest in using copper pillar wafer-to-wafer technology. Ideally, the wafers are flat, and the chip sizes are not very large, allowing for high-quality reflow for some of these spacings. While this presents some challenges, it is much less costly than committing to copper hybrid bonding technology. However, if the precision requirement is 10 microns or lower, the situation changes. Companies using chip stacking technology will achieve single-digit micron spacings, such as 4 or 5 microns, and there is no alternative. Therefore, the relevant technology will inevitably develop. However, existing technologies are also continuously improving. So now we are focusing on the limits to which copper pillars can extend and whether this technology will last long enough for customers to delay all design and "qualification" development investments in true copper hybrid bonding technology.
Chen: We will only adopt relevant technologies when there is demand.
Are there many new developments in the epoxy molding compound field currently?
Kelly: Molding compounds have undergone significant changes. Their CTE (coefficient of thermal expansion) has been greatly reduced, making them more favorable for relevant applications from a pressure perspective.
Otte: Returning to our previous discussion, how many semiconductor chips are currently manufactured with 1 or 2 micron spacing?
Kelly: A significant proportion.
Chen: Probably less than 1%.
Otte: So the technology we are discussing is not mainstream. It is not in the research phase, as leading companies are indeed applying this technology, but it is costly and has low yields.
Kelly: This is mainly applied in high-performance computing. Nowadays, it is used not only in data centers but also in high-end PCs and even some handheld devices. Although these devices are relatively small, they still have high performance. However, in the broader context of processors and CMOS applications, its proportion remains relatively small. For ordinary chip manufacturers, there is no need to adopt this technology.
Otte: That’s why it is surprising to see this technology entering the automotive industry. Cars do not need chips to be extremely small. They can remain at 20 or 40 nanometer processes, as the cost per transistor in semiconductors is lowest at this process.
Kelly: However, the computational requirements for ADAS or autonomous driving are the same as those for AI PCs or similar devices. Therefore, the automotive industry does need to invest in these cutting-edge technologies.
If the product cycle is five years, could adopting new technologies extend the advantage for another five years?
Kelly: That’s a very reasonable point. The automotive industry has another angle. Consider simple servo controllers or relatively simple analog devices that have been in existence for 20 years and are very low-cost. They use small chips. People in the automotive industry want to continue using these products. They only want to invest in very high-end computing devices with digital small chips and possibly pair them with low-cost analog chips, flash memory, and RF chips. For them, the small chip model makes a lot of sense because they can retain many low-cost, stable, older generation parts. They neither want to change these parts nor need to. Then, they just need to add a high-end 5-nanometer or 3-nanometer small chip to fulfill the functions of the ADAS portion. In fact, they are applying various types of small chips in one product. Unlike the PC and computing fields, the automotive industry has a more diverse range of applications.
Chen: Moreover, these chips do not have to be installed next to the engine, so the environmental conditions are relatively better.
Kelly: The environment temperature in cars is quite high. Therefore, even if the chip's power is not particularly high, the automotive industry must invest some funds in good thermal management solutions and may even consider using indium TIM (thermal interface materials) because the environmental conditions are very harsh.
Post time: Apr-28-2025